FIG. 8 is a circuit diagram illustrating a prior art high-pass/low-pass phase shifter. In the figure, a phase shifter 600 comprises two SPDT (Single Pole Double Throw) switches 2 and 26, a low-pass filter 8, and a high-pass filter 9. The low-pass filter 8 is interposed between a first output terminal 3 of the SPDT switch 2 and a first input terminal 27 of the SPDT switch 26. The low-pass filter 8 comprises two inductors 13 and 15 connected in series and a capacitor 14 interposed between the junction of the inductors 13 and 15 and ground. The high-pass filter 9 is interposed between a second output terminal 4 of the SPDT switch 2 and a second input terminal 28 of the SPDT switch 26. The high-pass filter 9 comprises grounded inductors 16 and 18 and a capacitor 17 interposed between the inductors 16 and 18. In this circuit, an input terminal 1 of the SPDT switch 2 and an output terminal 25 of the SPDT switch 26 serve as input and output terminals of the whole circuit.
The SPDT switch 2 includes FETs (Field Effect Transistors) 2a to 2d and resistors 2e to 2h of several k.OMEGA.. A gate bias terminal 6 is connected to gates of the FETs 2a and 2d, and a gate bias terminal 7 is connected to gates of the FETs 2b and 2c. The SPDT switch 26 includes FETs 26a to 26d and resistors 26e to 26h of several k.OMEGA.. A gate bias terminal 30 is connected to gates of the FETs 26a and 26d, and a gate bias terminal 31 is connected to gates of the FETs 26b and 26c.
A description is given of the operation.
Initially, the FETs 2a and 2d are turned on by a gate bias voltage applied to the gate bias terminal 6, the FETs 2b and 2c are turned off by a gate bias voltage applied to the gate bias terminal 7, the FETs 26a and 26d are turned on by a gate bias voltage applied to the gate bias terminal 30, and the FETs 26b and 26c are turned off by a gate bias voltage applied to the gate bias terminal 31, whereby the first output terminal 3 of the SPDT switch 2 and the first input terminal 27 of the SPDT switch 26 are selected. In this state, a signal applied to the input terminal 1 travels through the first output terminal 3 of the SPDT switch 2, the low-pass filter 8, and the first input terminal 27 of the SPDT switch 26, and it is output from the output terminal 25. At this time, the transmission phase of the signal from the input terminal 1 to the output terminal 25 is delayed, and a variation (8) in the phase represented by the following formula (1) is produced. ##EQU1## where XN is the normalized reactance of the inductors 13 and 15, and BN is the normalized susceptance of the capacitor 14.
Then, the FETs 2a and 2d are turned off by a gate bias voltage applied to the gate bias terminal 6, the FETs 2b and 2c are turned on by a gate bias voltage applied to the gate bias terminal 7, the FETs 26a and 26d are turned off by a gate bias voltage applied to the gate bias terminal 30, and the FETs 26b and 26c are turned on by a gate bias voltage applied to the gate bias terminal 31, whereby the second output terminal 4 of the SPDT switch 2 and the second input terminal 28 of the SPDT switch 26 are selected. In this state, a signal applied to the input terminal 1 travels through the second output terminal 4 of the SPDT switch 2, the high-pass filter 9, and the second input terminal 28 of the SPDT switch 26, and it is output from the output terminal 25. At this time, the transmission phase of the signal from the input terminal 1 to the output terminal 25 is advanced, and a variation (.theta.') of the phase represented by the following formula (2) is produced. ##EQU2## where Bn is the normalized susceptance of the inductors 16 and 18, and Xn is the normalized reactance of the capacitor 17.
As described above, in the prior art high-pass/low-pass phase shifter, the SPDT switches 2 and 26 select one of the two signal transmission paths from the input terminal 1 to the output terminal 25, i.e., the path through the low-pass filter 8 and the path through the high-pass shifter 9, whereby two phase quantities, i.e., one phase shift quantity, are obtained.
In the prior art high-pass/low-pass phase shifter, however, only one phase shift quantity is obtained in one phase shifter. Therefore, when a multiple bit phase shifter is fabricated using the high-pass/low-pass phase shifter, a plurality of the high-pass/low-pass phase shifters that are designed to have different phase shift quantities must be connected in series, increasing chip size. Further, the number of the SPDT switches increases with an increase in the bit number, whereby the signal transmission loss increases.